Speculative Lookahead for Energy-Efficient Microprocessors

Abstract

In addition to being the in situ performance monitor for adaptive voltage scaling (AVS), timing speculation mechanisms (e.g., razor) featuring dynamic timing fault detection and correction help to relax timing constraints for simple logic structures and low-power cells. Conventional timing fault detection mechanisms require substantial buffers to prevent race conditions on short paths for double sampling, which can overwhelm energy savings from timing relaxation and voltage scaling. This paper proposes a novel timing speculation scheme, speculative lookahead (SL), comprising duplicate timing-relaxed datapaths, the short paths of which do not introduce race conditions and thus require no additional buffer insertion. In experiments using a 40-nm CMOS technology, SL consumed a 54.89% area of a razor-based 32-bit multiplier, and conserved 59.77% energy per operation at nominal 1.1 V and 53.49% when AVS was applied. An ARM Cortex M0-like microprocessor unit (MPU) was designed using an SL-based datapath, the timing fault detection and correction mechanism of which can be dynamically deactivated for latency-tolerant instructions [i.e., on-demand timing speculation (ODTS)] to further conserve up to 31.08% energy in the execution unit. In addition, an field-programmable gate array prototype of the SL/ODTS MPU was constructed to demonstrate the effectiveness of delay variation tolerance and implementation flexibility.