Abstract
Source/Drain (S/D) dopant concentration related reliability issues including erase speed degradation, sub-threshold swing (SS) increase, and program/erase (P/E) cycling induced low threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) state drift and on-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) reduction are carefully examined in charge trapping (CT) NAND flash memories. Residual charges above S/D junctions has been identified as a dominant factor and cell performances are greatly improved with increasing S/D dosages. Moreover, a new program disturbance behavior, which possibly originates from junction leakage or breakdown induced hot carriers injection, is observed. Simulation results confirm that a high lateral junction field occurs at a program-disturbed cell once its S/D is fully depleted. Although optimizing S/D dosage can ease this situation, it is still a possible obstacle for further device scaling.
Published Version
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