Read Disturbs in Triple-Level-Cell (TLC) 3D Charge-trap (CT) NAND Flash Memory

Abstract

Read Disturbs (RD) is a key reliability issue for NAND flash memory applications in hot storages. In traditional 2D NAND flash memory, RD caused error bits originate from the leakage currents via the tunneling oxide, which degrades when the cells suffer from repeated Program/Erase (P/E) cycling. In vertical 3D NAND flash memory, RD properties are quite different from its 2D counterpart, showing different dependences on read numbers, P/E cycling and even the data retention (DR) time. In this report, the underlying physical mechanism are investigated on the basis of comprehensive characterizations of triple-level-cell (TLC) 3D charge-trap (CT) NAND flash memory chips. Furthermore, several approaches will be introduced to suppress RDs in 3D NAND flash, showing that part of error bits from RD can be effectively recovered by optimizing the operation schemes. These results are important for robust reliability designs of NAND-based hot storage applications. (Acknowledgments: This work is supported by China Key Research and Development Program #2016YFA0201802, and the National Natural Science Foundation of China #61874068)