Source/Drain Epitaxy for Nanosheet-Based CFET Devices

Abstract

This work reports the progress in source/drain (S/D) epitaxy development for nanosheet-based monolithic complementary field effect transistors (mCFET). S/D processes which were set-up for bulk finFET devices can be easily transferred to mCFET devices. Owing to the complicated integration and small dimensions of the highly scaled structures however, more attention is required for the pre-epi cleaning of the exposed channel interfaces and for the additional defectivity that arises from the merging of individual epitaxial growth fronts. Low-temperature epi processes can be structurally integrated in mCFET devices, to further reduce the transistor access resistance components and comply with thermal budget limitations.