Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process

Abstract

The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate to differential FF designs. With the small magnitude of input voltages (and the resulting small noise margins) needed for proper operation, sense-amplifier based FF designs (SAFF) are susceptible to single-event effects (SEE). Single event upset (SEU) performance of high-speed SAFF designs is investigated in this paper for 16-nm bulk FinFET CMOS technology. SEU cross-sections for SAFF are evaluated over particle LET, temperature, and operating frequency. Results show significant increases in cross-sections as a function of frequency, but not so for temperature. Results presented in this work can guide designers to harden the SAFF that satisfies their specific circuit SEU error rate constraints.