SEU Performance of RHBD Flip-Flops Using Guard Gates at 22-nm FDSOI Technology Node

Abstract

Because of the isolation of transistors, fully-depleted silicon-on-insulator (FDSOI) technology nodes have shown better single-event upset (SEU) resilience compared with bulk technology nodes. Additional radiation-hardening-by-design (RHBD) techniques can further improve the SEU performance. In this paper, SEU performance of multiple RHBD flip-flop (FF) designs using the guard-gate circuit at a 22-nm FDSOI technology is presented, including a conventional FF, a guard-gate (GG) FF, a dual-feedback-recovery (DFR) FF, and a GG-Dual-Interconnected Storage Cell (DICE) FF. Irradiation results showed significant reductions in SEU cross-sections for hardened designs compared to the conventional design. Specifically, the conventional GG design demonstrates more than 100X improvement over a conventional FF design, while DFR and GG-DICE designs showed no upsets for all test conditions. Further analysis was carried out to explain the SEU performance differences between the GG and DFR FF designs, and it is noted that proper layout arrangement is critical for achieving ideal SEU mitigation in this FDSOI technology node.