Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology

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The comparator is a key component of analog to information converters. The speed and the accuracy of the comparator determine the conversion quality. As device-scaling enters in the nanometer dimensions, the circuit becomes more susceptible to temporary faults. In this work, Single-Event Transient effects on a dynamic comparator in 28 nm FDSOI CMOS technology are investigated. The sensitivity of the circuit is simulated combined with the polarity of differential inputs and the working phases of the comparator. Moreover, the body-bias and the transistor channel modulation impact were analyzed. The minimum charge Qc to produce incorrect outputs is determined according to the striking time and the transistor involved by the strike. Results show that circuit vulnerability is a function of the individual transistor, the striking time, body-bias and the transistor channel modulation. Moreover, the minimum Qc value increases by 4.3% and 12.4% using the poly technique and the flip-well with back-bias configuration, respectively.