Abstract
A commonly used organization for built-in self-test of VLSI (very large-scale integration) circuits uses complete or pseudorandom test input generators followed by output data reduction. Two compression techniques which have been used are polynomial division (signature) and ones counting (syndrome). The simultaneous use of both of these approaches in parallel is investigated. Analytic and enumerative results indicate that the number of error patterns which are missed by both methods together is nearly the theoretical minimum. The conclusion extends to signature compression combined with any other counter-based compression method such as the use of Walsh spectral coefficients. Some suggestions for CAD (computer-aided design) implementations of test design are given based on these results. >
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