Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5-nm CMOS Applications

Talib Al-Ameri,Vihar P. Georgiev,Asen Asenov,Fikru Adamu-Lema

doi:10.1109/jeds.2017.2752465

Abstract

In this paper, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5-nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson-Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5-nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this paper.

Highlights

In recent years, the Fin field effect transistor (FinFET) has been introduced as a technology solution designed to tackle the challenges facing the semiconductor industry, such as high leakage current, short-channel effects, and performance degradation in extremely scaled planar MOSFETs [1], [2]
In this paper, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5-nm CMOS technology
Those results are compared to the target drive current (1.58 mA/μm) for the 5 nm CMOS, which we evaluate in the introduction of this work

Summary

Introduction

The Fin field effect transistor (FinFET) has been introduced as a technology solution designed to tackle the challenges facing the semiconductor industry, such as high leakage current, short-channel effects, and performance degradation in extremely scaled planar MOSFETs [1], [2]. The 7 nm FinFETs are under intensive development [3]. To continue to maintain the scaling of the technology the FinFET size must be reduced significantly [4]. Scaling down the fin width of the FinFET increases the process variability and the device’s statistical variability [5]. In order to improve the drive current the fin must be taller and narrower, making it very hard to control the channel shape and geometry. Further scaling of the FinFET transistors will be extremely challenging

Methods

Results

Conclusion