Vertically stacked lateral Si80Ge20 nanowires transistors for 5 nm CMOS applications

Abstract

In this work we present a simulation study of Si80Ge20 and Silicon vertically stacked lateral nanowires transistors (NWTs) with potential application at 5nm CMOS technology node. Our simulation approach is based on careful selection of simulations techniques in order to capture the complexity of such ultra-scaled devices. We have used ensemble Monte Carlo (MC) simulations to accurately predict the drive current considering the complexity of the carrier transport in the NWTs. We have used also drift-diffusion (DD) simulations with quantum corrections based on Poisson-Schrodinger solution to accurately calibrate the density-gradient based DD quantum corrections. Finally, we have benchmarked the current in Si80Ge20 NWTs against Si based NWT.