Abstract
An observation was made in this research regarding the fact that the signatures of isotropic charge distributions in silicon nanowire transistors (NWT) displayed identical characteristics to the golden ratio (Phi). In turn, a simulation was conducted regarding ultra-scaled n-type Si (NWT) with respect to the 5-nm complementary metal-oxide-semiconductor (CMOS) application. The results reveal that the amount of mobile charge in the channel and intrinsic speed of the device are determined by the device geometry and could also be correlated to the golden ratio (Phi). This paper highlights the issue that the optimization of NWT geometry could reduce the impact of the main sources of statistical variability on the Figure of Merit (FoM) of devices. In the context of industrial early successes in fabricating vertically stacked NWT, ensemble Monte Carlo (MC) simulations with quantum correction are used to accurately predict the drive current. This occurs alongside a consideration of the degree to which the carrier transport in the vertically stacked lateral NWTs are complex.
Highlights
IntroductionDespite the availability of numerous studies that have sought to measure natural instances of the golden ratio, a publication has yet to emergence addressing the effect that Phi has on the central parameters and performance of nano transistors, including gate all around (GAA) nanowire transistors (NWTs) [2]
The golden ratio is noteworthy for a variety of reasons: firstly, it can be observed in many naturally occurring patterns, artistic works, and mathematical phenomena; and secondly, in more recent years, the literature has uncovered specific nanoscale symmetry concealed within solid state matter, which reflects aspects of the golden ratio [1].Despite the availability of numerous studies that have sought to measure natural instances of the golden ratio, a publication has yet to emergence addressing the effect that Phi has on the central parameters and performance of nano transistors, including gate all around (GAA) nanowire transistors (NWTs) [2]
The present paper represents a valuable contribution to the literature, since it is the first
Summary
Despite the availability of numerous studies that have sought to measure natural instances of the golden ratio, a publication has yet to emergence addressing the effect that Phi has on the central parameters and performance of nano transistors, including gate all around (GAA) nanowire transistors (NWTs) [2]. As illuminated in studies such as [3,4], GAA NTWs constitute a promising device architecture that are anticipated to be used for technological advancement in the domain of nodes. Owing to their favorable property of electrostatic integrity, GAA NTWs have been marked as one of the successors of Fin field effect transistor (FinFET) technology in the 5-nm technology node. It is possible to establish an ideal compromise between leakage currents and GAA NTW performance by engineering device structures.
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