Simulation study of the noise figure of nanometer-gate nMOS transistors near the scaling limit

Abstract

We present a comprehensive simulation study of the noise figure of the nMOS transistors embedded in a common-source low noise amplifier (LNA) configuration using bulk 40- and 20-nm nMOSFETs, a 20-nm double-gate (DG) nMOSFET (a generic form of FinFET), and a 10-nm DG nMOSFET near the scaling limit. A physics-based two-dimensional (2-D) mixed-mode simulation approach is used to extract the noise parameters at 60 GHz. Minimum noise measure figure (NMF min) is used to take both the amplifier gain and noise figure into account. The optimal gate bias for a nMOS transistor is found to be 0.2–0.3 V above the threshold voltage. The 40-nm nMOS amplifier has a minimum noise measure figure of 1.8 dB at 60 GHz under the optimized power using current silicide technology. It is shown that the noise performance of CMOS LNAs can be further enhanced by down scaling to 10 nm with sub-1 dB noise figure at 60 GHz.