Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology

Abstract

An ESD TCAD Workbench with a library of ESD and Latchup devices and circuits has been developed in a 32 nm bulk CMOS technology. The devices which were developed from process and layout information were calibrated to experimental results in the low current DC and high-current/high-temperature ESD regime. The failure currents of ESD devices correlated to the experimental data to within 15% and the failure location of the devices in TCAD were confirmed using failure analysis.