Abstract
In this work, a kind of negative capacitance double-gate junctionless transistor (NC-DG-JLT) with ferroelectric (FE) gate dielectric and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure is proposed. It is demonstrated that NC-DG-JLTs can lower off-state current, improve on-state drain current, and lower subthreshold swing at the same time compared with its conventional DG JLT counterpart using numerical simulation. The steep subthreshold swing (SS<60mV/dec) is achieved at room temperature. The related physical mechanisms are discussed in detail. The low off-state current and high on/off current ratio could be obtained even for ultra-small transistors by optimizing the device parameters. NC-DG-JLTs have a great potential for low power dissipation applications.
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