SILC decay in La 2O 3 gate dielectrics grown on Ge substrates subjected to constant voltage stress

Abstract

The effect of constant voltage stress (CVS) on Pt/La 2O 3/ n-Ge MOS devices biased at accumulation is investigated and reported. It is found that the stress induced leakage current (SILC) initially increases due to electron charge trapping on pre-existing bulk oxide defects. After 10 s approximately, a clear decay of SILC commences which follows a t − n power law, with n lying between 0.56 and 0.75. This decay of SILC is not changed or reversed when the stressing voltage stops for short time intervals. The effect is attributed to the creation of new positively charged defects in the oxide because of the applied stressing voltage, while other mechanism such as dielectric relaxation proposed in the past is proved insufficient to explain the experimental data. Also high frequency capacitance vs. gate voltage ( C– V g ) curves measured under different CVS conditions divulge the creation of defects and charge trapping characteristics of La 2O 3 preciously. At low CVS exemplify the generation positively charged defects, however at higher CVS charge trapping obeys a model that was previously proposed and is a continuous distribution of traps.