Abstract
In binary digital computers addition is performed employing the carry propagation technique, which essentially limits the computing speed. For multiplication the speed is further reduced because of the number of shift and add operations. To alleviate this problem, a modified signed-bit (MSD) number system has already been proposed. The inher- ent parallel architecture of optical processors makes the best use of the carry-free features of MSD binary numbers. In this paper, we use a very large scale integration SLM and CCD detector to demonstrate truth table lookup for carry-free MSD addition. © 2001 Society of Photo-Optical Instrumen- tation Engineers. (DOI: 10.1117/1.1412615)
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