Abstract

The problems of achieving parallel arithmetic has been investigated by many authors using residue number system, modified-signed digit (MSD) number system and recoded MSD systems.1,2 Using residue arithmetic, one can perform parallel arithmetic in constant time using symbolic substitution (SS), but the size of the truth table required increases rapidly with the increase of the operand length. The MSD representation has been widely studied for implementing parallel optical arithmetic. Recently, we proposed a higher-order MSD technique2 for parallel arithmetic using SS. This technique2 performs carry-free addition and borrow-free subtraction by checking a pair of reference digit from the next lower order bit position. However, MSD representation requires negative representation of a literal. Most recently, a redundant binary number representation3 has been proposed for parallel arithmetic using only two literals, 0 and 1. For long bit strings, this scheme3 doubles the operand length. To overcome the aforementioned problems, we propose the recoded trinary arithmetic processing technique which performs multibit carry-free addition and borrow-free subtraction in constant time by employing a two-step SS scheme. In the first step, a set of SS rules are applied to the pair of numbers to be added into an intermediate pair. Subsequent application of the SS rules to the intermediate pair of numbers yields the result. This technique also leads to a compact design by incorporating more information in fewer digits using a higher radix number system.

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