Abstract
Increased frequencies and reduced rise times have made signal integrity simulations an integral part of high speed board designs. Signal integrity simulations are usually performed considering an ideal power source and power integrity simulations are performed assuming ideal transmission lines. But due to ever decreasing rise times errors creep into signal quality and timing analysis by ignoring the effects of the PDN. This paper outlines the necessity and the impact of including power delivery network effects for signal quality and timing analysis. This paper highlights the combined effort of signal integrity and power delivery simulations which are performed to obtain the optimal topology, terminations and decoupling solution for motherboard implementation of 533MT/s DDR2 devices that are soldered directly on the motherboard
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