Shock performance study of solder joints in wafer level packages

Abstract

In this paper, an integrated testing, finite element modeling and failure analysis approach for drop test reliability of wafer level packages is developed to examine the shock performance of large array wafer level packages. For standard JEDEC drop test, it has been found that corner component group (group A) failed first for 12 times 12 array packages. This is different from previously reported failure test data of BGA packages. Careful analysis concluded that the high failure rate of group A is mainly due to the effect of mounting screws rather than the intrinsic strength of the package. For a given WLP, corner balls always fail first during drop test. The crack initiates at inner side of the solder joint and propagate towards the opposite side. The primary failure is always on the intermetallic compound (IMC) at WLP side. It has been found that drop reliability significantly decreases with array size increasing. Novel finite element modeling approach has been developed to correlate with experimental data. The finite element model was validated with experimental board strain data, and frequency analysis. In-plane principal strain at corner locations and maximum peeling stress in IMC at critical solder joints are used to correlate with experimental data. Excellent agreement was reached to predict the failure rate of components in each group. Two new findings have been observed and validated. One is that existing JEDEC board design will lead group A components fail first for certain array size of wafer level packages. Another finding is that PCB board strain does not always correlate with maximum peeling stress in solder joints when array size changes.