Larger Array Fine Pitch Wafer Level Package Drop Test Reliability

Abstract

In this study, drop test reliabilities of wafer level packages (WLP) are investigated. Failure mechanism, crack map and crack initiation location are presented. Failure rates of six groups defined by JEDEC are examined through both drop test experiment and finite element (FE) analysis with ANSYS software. Effects of component placement, PCB design, WLP structures, array size, pitch, and solder alloy are studied through drop test experiment per JESD22-B111 and finite element modeling. It is found that the primary failure mechanism of WLP drop test failures is fracture of intermetallic compound (IMC) at WLP side. During the drop test, solder joints at outer columns experience most stress and will fracture first. And the corner balls always fail first. The crack initiates at inner side of solder joint and propagates to the opposite side. When JEDEC recommended PCB is used for WLP drop test, the corner components fail first. This is different from the findings from BGA packages. It is confirmed that the dominant failure rate of corner WLP components is mainly due to the effect of mounting screws, rather than the intrinsic drop test reliability of WLP. Therefore, it is not appropriate to judge the drop test reliability of WLP with the drop test data for the corner components. Instead, middle component drop test data represent intrinsic shock resistance of WLP, and they should be used to represent the drop test performance of WLP. Drop test DOE results showed that WLP structure and material make visible difference. Non-soldermask defined (NSMD) PCB pad designs result in better drop reliability than SMD pads. With a given ball array, WLP with smaller pitch has worse drop reliability. As array size increases from 6×6 to 10×10 and 12×12, the drop test performance drops significantly. In addition, choice of solder alloy makes visible difference for WLP.