Investigation of stress-buffer-enhanced package subjected to board-level drop test

Abstract

In this research, the objective is to develop a stress-buffer-enhanced package subjected to board level drop test under a high-G impact drop; both drop test experiments and ANSYS/LS-DYNA simulations are executed. Many researchers indicate that solder joints in wafer level chip scale package (WLCSP) are the weakest portion in board-level drop test because of the large relative motion between the board and the chip mounted on it and the brittle intermetallic compound (IMC) layer. To compare with the failure mechanism of traditional WLCSP structure, the stress-buffer-enhanced package shifts its failure mode to the trace damage on the chip side. Because the soft stress buffer layer has relatively larger elongation to reduce the impact to the solder joints, the corner between the solder joints and connection trace becomes the critical region which may break due to the stress concentration effect. In the drop test experiment, the proposed stress-buffer-enhanced package passed over 100 drops (most packages passed 240 drops); the performance far exceeds the JEDEC criterion which is 30 drops. Following, three phases of drop test simulation are conducted to elucidate the mechanical behavior of board and packages during the blink of impact. Results show that the stress at proposed stress-buffer-enhanced package is much smaller than that at conventional WLCSP. On the other hand, the trace stress level of proposed stress-buffer-enhanced package is slightly larger than that of conventional WLCSP. Simulation results explain the impact loading absorption of thick dielectric layer to reduce the stress level of solder joints.