Sequential Parallel Switching for Drain-Source Synchronous Rectifier Efficiency and Light-Load Stability Improvement

Abstract

Drain-source synchronous rectification (SR) is a technique used to reduce the secondary-side conduction loss of an LLC resonant converter. In drain-source sensed SR, an early turn off issue can be observed due to parasitics in the drain-source voltage sensing loop. In LLC converter rectifiers where multiple SR switches are paralleled, sequential parallel switching (SPS) can be implemented to sequentially turn off the SR FETs to reduce the effect of these parasitics. By turning off SR FETs one by one over batch turn-off, the drain-source voltage signal near the turn-off moment can be enhanced, mitigating the effects of parasitics and the subsequent early turn-off issue. This method also reduces the amount of turn-off jitter experienced with low on-resistance (R DS,on ) FETs, which can start a detrimental resonance at light load conditions. Since the SR conduction time is prolonged, SPS can decrease body-diode/anti-parallel-diode conduction loss in the rectifier. This results in a net increase in converter efficiency, despite a slight increase in the SR FET’s channel conduction loss. The concept and operation of SPS is proposed, explained, and simulated in this paper. Finally, SPS is implemented and verified at light load on a LLC resonant converter with paralleled GaN SR FETs.