Cyclically Adaptive Multilevel Gate Driving for Drain-Source Synchronous Rectifier Efficiency Improvement and Range Extension

Abstract

In unidirectional LLC converters, synchronous rectification (SR) is a technique that can be implemented to minimize the conduction loss of the secondary-side LLC rectifier. In drain-source voltage-sensed SR, a premature turn off issue can be observed due to parasitics present in the drain-source voltage sensing loop. In this digest, a novel use of multilevel gate drivers (MLGDs) and digitally adaptive control for multilevel turn-off can be implemented to mitigate parasitic effects, boost efficiency and the applicable load range of drain-source SR. Multilevel gate driving boosts the sensed SR signal strength, extending the total SR conduction period. This driver can be combined with an adaptive delay block to maximize efficiency. Because the increased drain-source signal integrity is increased at the turn-off moment, this also prevents an oscillation issue at light loads. Overall rectifier efficiency is increased over a traditional gate driver or non-adaptive MLGD due to a reduction in parallel diode conduction from tuning the transition point. The concept of the adaptive multilevel gate driver is proposed, explained, and simulated in this paper. A discrete multilevel gate driver is built and an adaptive delay block designed in a FPGA and tested on a LLC-DCX resonant converter for proof of concept.