Abstract
Drain-source voltage-sensed synchronous rectification (SR) is a technique used that can be used to reduce the secondaryside diode conduction loss of an LLC converter. In drain-source SR, an early SR-switch turn off issue is observed due to parasitics present in the power path of the rectifier drain-source sensing loop. In rectifiers with parallel switches, sequential parallel switching (SPS) can be utilized to increase the drain-source signal integrity near turn off. In rectifiers where a single SR switch is used, multilevel turn-off can be used to reduce the parasitic effects and allow for a more accurate SR turn-off. By reducing the gate voltage prior to SR turn-off, the drain-source voltage signal near the turn-off moment can be boosted to minimize the parasitic drain-source phase shift effect, extending the total SR conduction time. Multi-level turn off also reduces the amount of turn-off edge jitter experienced, which can start an internal unstable resonance at light-load conditions. By increasing the SR conduction time, multilevel turn-off can decrease body or antiparallel diode conduction loss in the LLC rectifier. This results in a net increase in total converter efficiency, despite a small increase in the SR FET channel conduction loss from the prolonged channel conduction time. A discrete three-level multilevel gate driver is built to test this concept, simulations are in the process of being run, and verification with silicon carbide SR FETs is performed on a 2.5kW LLC-DCX module.
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