Sensitive bits based prediction method of functional failure time for SRAM-based FPGA

Abstract

SRAM (Static Random Access Memory)-based FPGA (Field-Programmable Gate Array) is widely used in aircraft with its high-performance and reconfigurable characteristics. It has been proved that SRAM memory cells of the device are extremely sensitive to single particle effects of atmospheric neutrons. SEU (Single Event Upset) failure chain was proposed according to the SRAM-based FPGA three-tier architecture model and the failure mode of SEU. Sensitive factor was introduced to quantitatively describe the capability of anti-SEU of the device functional circuit. Later, failure propagation model was built to describe the propagation of SEU on the logical layer on the logical layer for complex circuit simulation. Fault injection experiments were performed to ISCAS85 test circuits based on the partial reconfiguration technology. Finally, a method was proposed to assess SEU mean functional failure time of the device under obtained sensitive bits in the experiments.