An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA

Abstract

Field programmable gate array (FPGA) is becoming more valuable for space applications because of its large density, high performance, reduced development cost and flexible programmability. In particular, static random access memory (SRAM) based FPGA is very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. However, SRAM-based FPGA contains a large number of memory cells which are very sensitive to single event upset (SEU). SEU in SRAM-based FPGA may result in a functional error unless the FPGA is reconfigured. In this paper, we propose a fast adjustable scrubbing method based on Xilinx essential bits technology to mitigate the effect of SEU for SRAM-based FPGA. The whole scrubbing flow contains two sub-flows: partial scrubbing and entire scrubbing. This scrubbing method not only increases the speed of repairing an error for user design, but also ensures the reliability of whole FPGA design. We test the proposed scrubbing method through fault injection. Finally, we show the error repair speeds of user designs for different repeat cycles of partial scrubbing and summarize the optimized repeat cycles of partial scrubbing.