Abstract
In the semiconductor industry, many previous optimization studies have been carried out at the integrated circuit front-end design phase to identify optimal circuit elements’ size and design parameters. With the scaling of device dimensions, semiconductor manufacturing back-end Final Test (FT) yield is increasingly influenced by systematic or random process variations. As a result, the FT yield is not fully guaranteed by design phase optimization due to existing limitations of yield simulation models and coverage. Very few studies have attempted to incorporate the production FT yield data into process variation optimization and inverse design. In this paper, we introduce a novel framework for FT yield optimization and Wafer Acceptance Test (WAT) parameter inverse design using multi-objective optimization algorithms. This provides a solution to monitor and quickly adjust process variations to maximize FT yield without expensive characterization or design correction after products are released into the production phase. Both yield optimization and process shift feasibility are to be taken into consideration by formulating these factors into a two objective optimization problem. One objective is to minimize FT yield loss, wherein the yield loss is predicted by a machine learning model. The other objective is to minimize the total WAT parameters shift distance from the current standard setting. Three widely used multi-objective algorithms NSGA-II, SMPSO and GDE3 are applied, compared and discussed. An automatic parameter tuning approach using Sequential Model-based Algorithm Configuration (SMAC) and entropy-based termination criterion is applied to reduce the execution time whilst maintaining the optimization algorithms’ performance. Real production data for CMOS 55nm chip are used to validate the framework and the results point to the effectiveness of yield improvement and accurate identification of the optimal WAT parameter combination.
Highlights
W Ith the increasing cost of semiconductor fabrication due to technology node shrinking and global supply shortage situations, the manufacturing yield optimization is becoming one of the most critical goals for semiconductor operations
We introduce a novel framework for Final Test (FT) yield optimization and Wafer Acceptance Test (WAT) parameter inverse design using multi-objective optimization algorithms
We propose a novel framework for semiconductor manufacturing Final Test (FT) yield optimization through inverse design for the Wafer Acceptance Test (WAT) parameters
Summary
W Ith the increasing cost of semiconductor fabrication due to technology node shrinking and global supply shortage situations, the manufacturing yield optimization is becoming one of the most critical goals for semiconductor operations. In the work of Kim et al [16], DE is again applied to determine the chip size and optimize wafer productivity The limitation of these studies is that through a single objective optimization, only a single Pareto result can be generated in each simulation. In [15], a tree-based model is introduced to maximize the number of gross dies and increase the wafer fabrication throughput The limitation of this method is that the optimization procedure is time consuming and require engineers’ knowledge to decide on the search areas. To the best of our knowledge, this is the first study aimed at improving semiconductor manufacturing FT yield through WAT parameter inverse design by means of using multi-objective optimization algorithms. Trade-offs between yield improvement and allowable process shift will be considered during the optimization, which helps engineers making proper decisions based on each objective’s relative importance in the practical situation
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
