A Gaussian Mixture Model Clustering Ensemble Regressor for Semiconductor Manufacturing Final Test Yield Prediction

Dan Jiang,Weihua Lin,Nagarajan Raghavan

doi:10.1109/access.2021.3055433

Dan Jiang, Weihua Lin + Show 1 more

Open Access

https://doi.org/10.1109/access.2021.3055433

Copy DOI

Abstract

In the semiconductor industry, many studies have been carried out for front-end related process improvement and yield prediction using machine learning techniques. However, very few research investigations have dealt with the backend Final Test (FT) yield prediction using the front-end wafer acceptance test (WAT) parameters. The manufacturing cycle time between wafer fabrication (WF) and FT can range anywhere between a few weeks to several months. It is therefore important for semiconductor manufacturers to detect wafer material related low yield problems at an earlier stage for effective cost and quality control. This is a challenging goal as the input data used for prediction is at a very early manufacturing stage and the output FT yield for packaged chips is the last stage of the fabrication chain. There are many unknown production variations caused by different manufacturing processes, equipment configurations and human interferences in this multi-stage sequential fabrication chain. In this paper, we proposed a novel procedure to predict the backend FT yield at the WF stage itself using a Gaussian Mixture Models (GMM) clustering approach that is applied to build a weighted ensemble regressor. Real production data for new chip product lines are verified with this method and show significant improvement in the prediction performance.

Highlights

In today’s competitive semiconductor industry where huge amount of data are generated every day from hundreds to thousands of manufacturing process steps, advanced data analytics solutions are gaining increasing importance to improve capacity, quality and efficiency
RELATED WORK Previous semiconductor industry research explorations used machine learning techniques that were mainly focused on the front-end process related problems like virtual metrology (VM) improvements in Ref. [2], fault detection and classification in Ref. [3], wafer yield estimation in Refs. [4], [5], probe yield excursion detection and root cause analysis in Ref. [6], probe yield analysis based on wafer spatial features in Refs. [7], [8] and probe yield prediction with input parameters including electrical test parameters, wafer defect and wafer physical data [9], [10]
In this paper, we proposed a novel procedure to predict semiconductor manufacturing backend Final Test (FT) yield using the front-end wafer acceptance test (WAT) parameters using a suite of machine learning techniques

Summary

INTRODUCTION

In today’s competitive semiconductor industry where huge amount of data are generated every day from hundreds to thousands of manufacturing process steps, advanced data analytics solutions are gaining increasing importance to improve capacity, quality and efficiency. The front-end WAT measurements are used as input data to predict the back-end FT test yield This makes the problem more challenging compared to past research studies since the manufacturing process variation is not limited to the front-end process alone. Our tool is able to automatically identify and rank important WAT parameters and provide quick fix yield improvement strategies, thereby reducing (if not eliminating) the cost and time duration for DOE to be performed. This approach will enable significant manufacturing cost reduction and help monitor product quality, as well as improve shipment forecast accuracy.

RELATED WORK

YIELD PREDICTION PROCEDURE

RESULTS AND DISCUSSION

FEATURE IMPORTANCE ANALYSIS AND YIELD IMPROVEMENT VALIDATION

CONCLUSION