The development of a novel stacked package: package in package

Abstract

Stacked die chip scale packages (CSPs) or fine-pitch BGAs (FBGAs) have been readily adopted and integrated in many handheld products, most notably cellular phones. Such stacked die CSPs are especially useful to reduce the cost, weight, and size of the memory devices needed to support the increased features and applications in cellular phones today. In addition, they have been used extensively to integrate some logic and analog functions. In these cases, the die stacked in these CSP packages can be tested at the wafer level such that the final stacked die packaged electrical yield is well over 95%. This high final test yield and fairly low die cost makes such packages economical. However, combinations of devices to be integrated or stacked within a single CSP, in order to meet the needs of next generation cellular phone users, often require the die be fully functionally tested prior to packaging them together in order to assure good final test yield and cost. Known good die (KGD) are often difficult to source for such applications and are not always cost effective. In fact, a packaged and tested device can be less cost than a KGD. Therefore, it is desirable for a number of reasons to stack or integrate tested good packages within a CSP to meet the needs of such applications. This paper outlines the development of a novel stacked package CSP, called package in a package (PIP). In this PIP package, tested good packages are stacked and wire bonded much like the die in a conventional stacked die CSP. The same basic packaging infrastructure and package testing infrastructure is utilized. This paper shows the package level reliability of the PIP package is the same as the stacked die package today. Thus, there is no compromise in reliability and such PIP packages can meet lead free flow conditions. Stacked die CSPs have come to the fore for applications that require increased functionality, smaller form factors, and light weight. Stacked die CSP packages with two, three, four, and even five functional die are now available and in production. Primarily, memory die are stacked that are lower cost and can be well tested in wafer form prior to assembly to assure a cost effective final test yield. If a logic or ASIC die is stacked, it is usually paired with another device that can be tested good in wafer form, such that the final test yield is basically unaffected. However, the next generation of handheld products, most notably cellular phones, require significant amounts of high speed memory, such as SDRAM or DDR, to be paired with the microprocessor or ASIC. this type of high speed memory cannot be well tested easily in wafer form. Known good die (KGD) is needed for such devices, but KGD is costly and has limited availability and supplier base. In most cases, a tested good package is less costly and has less supply issues than a KGD. Thus, the need for a package that stacks good packages as oppose to wafer probed dice is evident.