Self-Timed Circuitry Retrospective

Abstract

The paper compares synchronous and self-timed methodologies for designing digital circuits. Self-timed circuits proposed by D. Muller in the mid-twentieth century have several advantages over synchronous counterparts. They maintain functional performance at any cell delays, do not require global synchronization, and identify constant failures. The data redundancy and associated hardware redundancy provide these self-timed circuit properties. The practical design of self-timed units of varying complexity has proven the effectiveness of self-timed solutions, especially in highly reliable and fault-tolerant applications. The paper presents the results of comparative measurements of test chips of synchronous and self-timed circuits, the performance, and immunity evaluations of self-timed circuits of different complexity levels. The proposed method of group indication of multi-bit self-timed circuits increases their performance by 40% due to a slight increase (less than 3%) in hardware complexity.