Abstract
The asynchronous design approach is an interesting alternative for modern System-On-Chip (SoC) designs because of its several benefits. Self-timed circuit have potential for low-power and low-noise design. Moreover, the modularity and the composability of asynchronous systems are favorable properties. This is partly due to the chips getting larger and denser, resulting in serious difficulties in the clock tree design. One of disadvantages has been the lack of commercial computer aided design (CAD) tools. This paper presents synthesis flow targeted for self-timed VLSI circuits provided by Handshake Solutions. The performance of the synthesis tool is compared with its synchronous counterpart in terms of area and speed. We have chosen to use cache controllers as case study.
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