Comparison of Synchronous and Self-Timed Pipeline’s Soft Error Tolerance

Abstract

The current trend in microelectronics is to develop energy-efficient, reliable digital devices for control and life support systems with various complexities. The operation of digital circuits in adverse environmental conditions causes the appearance of faults and short-term soft errors, leading either to stopping the circuit’s functioning or distorting the data processing results. The vast majority of digital circuits are synchronous, using a global clock signal to synchronize events and control the interaction of the overall circuit’s parts. Self-timed (ST) circuits are an alternative to synchronous ones. ST circuits are hardware redundant compared to synchronous counterparts and have several advantages. In particular, ST circuits have better soft error tolerance. The article analyzes the tolerance of synchronous and ST pipelines to a single soft error. The obtained quantitative comparative probability estimates of data processing result distortion in the pipeline due to a soft error in different pipeline stage’s parts prove that the ST pipeline is 2. 5-9.4 times less sensitive to single soft errors than its synchronous counterpart. Tripling a synchronous pipeline makes its complexity comparable to an ST pipeline but does not provide absolute protection against soft errors. Considering other advantages of the ST pipeline compared to the synchronous counterpart, improving its consumer characteristics, it is advisable to use the ST pipeline to implement reliable digital devices for critical applications.