Self-Timed Storage Register Soft Error Tolerance Improvement

Abstract

The paper examines the self-timed (ST) pipeline register’s tolerance to soft errors in the pipeline stage’s combinational part and in itself. It aims to analyze the known storage register bit’s circuit cases and improve its soft error tolerance. The use of failure tolerant ST coding, which treats the anti-spacer state as a spacer, increases the ST pipeline’s failure tolerance level. Layout techniques of spacing the dual-rail signal component sources at a distance of more than 2 µm from each other reduce the number of failure types in the ST circuits. In particular, switching the dual-rail signal from a correct working state to an inverse one becomes unrealizable. Circuitry techniques, including cross-connections and local feedback, prevent the bit of the ST-pipeline register from sticking in the anti-spacer state and significantly increase the register’s insensitivity to single soft errors. The use of a DICE-like C-element with two in-phase outputs instead of a known circuitry solution ensures the immunity of the register bit for soft errors inside it. All proposed techniques improve the ST circuit’s soft error tolerance level from 76% to 95%.