Abstract
A method of a self‐checking synchronous Finite State Machine (FSM) network design with low overhead is developed. Checkers are used only for FSMs, which output lines are at the same time output lines of the network. The checkers observe output lines of these FSMs. The method is based on reducing the problem to a self‐checking synchronous FSM design. The latter is provided by applying a special description of FSM namely, so‐called unate Programmable Logic Array (PLAu) description. Single stuck‐at fault on the FSM poles and gate poles are considered. PLAu realization of FSM allows a factorized or multilevel logic synthesis. They both provide a unidirectional manifestation of the above mentioned faults on the output lines of the corresponding FSMs. This realization also gives rise to a transparency of each component FSM of the network for the faults. PLAu realization is derived from the State Transition Graph (STG) description of FSMs with using the m‐out‐of‐n encoding of its states and insignificant expanding the products of STG. The problem of replacing an arbitrary synchronous FSM network for the self‐checking one with low overhead is discussed.
Highlights
A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead is developed
Our intention here is to design a self-checking synchronous FSM network so that checkers are used only for FSMs which output lines are at the same time the network output lines
Each checker observes the values of the FSM output lines but not both state and output lines as it was done in paper [7]
Summary
Outputs [1,2,3]. In the case when the functional block is a Finite State Machine (FSM), concurrent checking is usually based on outputs checking and on checking of the FSM transitions. Having applied either factorizing or multilevel logic synthesis to this system, we obtain the synchronous sequential circuit (SSC) that is a structural description of the self-checking FSM It is shown in paper [7] that for a specific fault model, which will be discussed below, the faults manifest themselves as unidirectional errors on the SSC combinational part output lines. The present paper is an attempt to combine the extended class of single stuck-at faults considered in [7] with observing only output lines of SSC considered in [6] It turned out in [8] that either factorizing or multilevel logic synthesis can be applied to the unate PLA (PLAu) description without loss of manifesting the above faults as unidirectional errors.
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