Self-aligned vertical p- n- p transistor: Device characterization from room to cryogenic temperatures

Abstract

High-performance p- n- p transistors have been fabricated utilizing the conventional self-aligned ion-implanted double-polysilicon approach. In the present profile and process design, heat cycle compatibility with the n- p- n transistor process was preserved. Device characteristics from room temperature down to cryogenic temperatures are presented. These transistors operated with high current gains of 47–57 at 300 K and ⩾ 10 at 84 K, respectively. Nearly ideal p- n-junction behavior with very low base leakage was observed over the entire temperature range. Excellent breakdown characteristics were also achieved. Under the active bias mode, no appreciable impact ionization current was detected for base-collector reverse voltage up to 5.25 V at all measurement temperatures. Devices built on this technology are suitable for broad-temperature-range and complementary-circuit applications.