Self-Aligned Offset-gated Poly-Si TFTs with Symmetric Source/Drain Characteristics

Abstract

We propose a new fabrication process for poly-Si thin film transistors in order to reduce leakage-current with a self-aligned offset-gated structure by employing a photo-resist reflow process. The new fabrication method makes the gate-oxide over the offset region with the assistance of sub-gate and reflowed photoresist. The new method does not require any additional offset mask step and the self-aligned implantation is applicable so that poly-Si TFT with the symmetrical offset length is easily fabricated. A symmetrical offset length from 0.7 µm to 2.3 µm is obtained successfully. The experimental results show that the maximum ON/OFF ratio is obtained with a considerable reduction in leakage-current when the offset length is 1.1 µm.