Self-aligned gate nanopillar In<inf>0.53</inf>Ga<inf>0.47</inf>As vertical tunnel transistor

Abstract

Tunnel field effect transistors (TFET) have gained interest recently owing to their potential in achieving sub-kT/q steep switching slope, thus promising low Vcc operation[1–5]. Steep switching slope has already been demonstrated in Silicon TFET [2]. However, it has been theoretically shown and experimentally proved that Si or Si x Ge 1−x based homo-junction or hetero-junction TFETs would not meet the drive current requirement for future low power high performance logic applications [3]. III–V based hetero-junction TFETs have shown promise to provide MOSFET like high drive currents at low operating Vcc while providing the sub-kT/q steep switching slope[1,4,5]. However, the device design demands extremely scaled EOT and ultra-thin body double-gate geometry in order to achieve the desired transistor performance [4]. In this paper, we discuss a vertical TFET fabrication process with self-aligned gate [6] which can ultimately lead to the ultra-thin double-gate device geometry in order to achieve the desired TFET performance.