Selective Area Growth: A Promising Way for Recessed Gate GaN MOSFET With High Quality MOS Interface

Abstract

Based on the selective area growth (SAG) technique, an enhancement mode GaN recessed gate MOSFET was fabricated successfully with negligible gate trapping effect, presenting an extremely small threshold voltage ( $V_{\mathrm {th}})$ hysteresis of 50 mV at a gate bias swing up to 10 V. Compared with the larger $V_{\mathrm {th}}$ hysteresis of a recessed gate GaN MOSFET fabricated by dry-etching, the correlation between the $V_{\mathrm {th}}$ hysteresis and the lattice damage related traps caused by plasma dry etching process has been confirmed. Furthermore, the SAG recessed MOSFET shows a lower turn-ON resistance due to the higher MOS channel mobility. We believe that all of these superior performance of SAG MOSFET are attributed to the damage free high quality GaN surface at the Al2O3/GaN MOS interface, which indicates that the SAG is a promising alternative technique toward stable GaN MOSFET for the power switching applications.