Abstract
The well-known trade-off between dc link voltage dynamics and ac-side current quality in power factor correction (PFC) rectifiers limits attainable dc link voltage loop bandwidth. It has been shown that adding a notch filter in series with the typically employed PI or type-II regulator allows improving dc link voltage dynamics without sacrificing total harmonic distortion (THD). However, clear quantitative guidelines for PI + Notch (PI + N) controller design to attain prescribed values of ac-side current THD and dc link voltage undershoot (response to a step-like load power increase) were not established so far. Consequently, analytical expressions linking the coefficients of the PI + N controller with the above-mentioned performance merits for a given value of dc link capacitance are revealed in this article. Corresponding dc link voltage loop gain phase margin and crossover frequency expressions are derived and the feasibility region of the proposed design guidelines is clearly indicated. Simulations and experimental results validate the proposed design methodology.
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