Guidelines for Voltage Controller Coefficients Design to Attain Prescribed Grid Current THD and DC-Link Voltage Undershoot Values in Power Factor Correction Front Ends

Abstract

This article establishes analytical guidelines for designing coefficients of proportional integral (PI) controller, typically used as voltage loop compensator of power factor correction rectifiers (PFCRs) operating in continuous conduction mode (CCM), based on two major performance merits (namely, total harmonic distortion (THD) of grid-side current and dc-link voltage deviation upon sudden load increase) and dc-link capacitance-to-rated power ratio. The proposed methodology allows to concretize the commonly used “5–10 Hz crossover frequency, 45°–70° phase margin” rule-of-thumb, typically used in application notes of commercial PFCR controllers. Explicit relationships between voltage loop gain crossover frequency and phase margin as well as settling time of dc-link voltage response to a step load increase to the above-mentioned performance merits are also derived in this article. Provided design guidelines allow to accurately achieve desired values of the two mentioned performance merits and indicate the feasible range of possible dc-link capacitance values. The proposed quantitative design guidelines are well-supported by experiments.