Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects

Abstract

Conventional clock guardbanding to assure a circuit’s reliable operation under device aging due to NBTI/PBTI and process variations introduce significant performance loss in modern nanometer circuits. Dynamic Frequency Scaling (DFS) is a more efficient technique that allows us to adjust the system clock frequency according to the process condition and aging deterioration of the circuit. At the design phase, the DFS technique requires the identification of the logic paths to be monitored to introduce the required circuitry to monitor their delay. However, critical path identification is a complex problem due to three major challenges: (1) The critical paths of the circuit depend on the stress duty cycle of the devices, which are unknown in advance at design phase; (2) the critical paths of the circuit depend on the process parameters variations, whose impact on delay depend on the spatial correlation due to proximity at the circuit layout; and (3) the critical paths reordering probability may change over time due to aging. This article presents a methodology for efficient selection of the critical paths to be monitored under a DFS framework, addressing the aforementioned challenges. Experimental results on ISCAS 85/89 benchmark circuits show the feasibility of the proposed approach to select a restricted path set while providing reliable aging monitoring.