Machine Learning Based Aging Critical Path Selection

Abstract

Under the current advanced semiconductor technology node, the aging of transistors becomes one of the main factors which affect the reliability of circuits. In order to cover the aging effect, the proper timing margins are usually added in the design according to the aging-aware timing analysis of the timing paths. However, the popular solution built on aging-aware SPICE simulation could hardly cover all the potential aging-critical paths due to its low operation speed. In this work, we developed a machine learning based classification system which could quickly complete critical path selection from a large number of paths. It extracts the path-level statistical features from the STA timing reports and invokes the integrated classifier which contains Random Forest Classifier, Support Vector Classifier and K-Nearest Neighbors Classifier to implement critical path (identified based on specific benchmarking threshold) selection. The verification results showed that the proposed system could classify about 1000 paths within 10 s, and the recall scores reach over 90% for various thresholds and process nodes. It is thought that the critical path selection scheme proposed in our work is well compatible with the current mainstream design flow and improves the aging analysis efficiency in the large design.