Abstract
Standard cryptographic System-on-Chip (SoC) design requires the development and reuse of Intellectual Property (IP) cores. These IP-cores often form the root-of-trust of several cryptographic protocols. However, just selecting a mathematically secure cryptographic algorithm and building an IP-core for it does not necessarily guarantee security. Owing to improper design methodologies, such IP-cores can be subjected to powerful attacks, which can lead to the collapse of overall security. Adversaries can observe physical information like power consumption, electromagnetic radiation, time required and using statistical techniques popularly called as side channel analysis (SCA) to get access to sensitive information. The IP-cores can also be subjected to perturbations (either accidental or malicious) to induce faults which can be exploited to recover the key used inside the cipher cores. Along with design, testing and validation of such IP cores also pose unique security challenges. Thus popular test methodologies useful for validating IP cores in conventional SOC designs, can in-turn be used for attacking the IPs. The chapter also discusses suitable countermeasures which can not only mitigate such threats, but also lay the foundations for future IP Design-for-Security.
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