Abstract
The design of a second-order digital phase-locked loop (DPLL) based on the time-delay digital tanlock loop (TDTL) architecture is presented. The proposed design simplifies the architecture of the TDTL by eliminating the requirement for the time delay block. In addition, the system includes a controller block whose output feeds into the arctan phase detector of the proposed system so as to optimize the acquisition time and/or the lock range of the loop. The system performance evaluation results show that it is possible to selectively optimize certain parameters of the system in order to match specific application requirements.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
