Time-delay Digital Tanlock Loop based demodulators in FPGA

Abstract

Hardware modulators employed in satellite digital communication systems handle various data formats such as CCSDS, modulation schemes, data rates and sub carrier frequencies. Real time verification of transmitted data during transmission, is a requirement to be met using an inbuilt demodulator chain. One such latest Data Modem Unit (DMU) development uses TDTL (Time Delay Digital Tanlock Loop) based demodulators for FSK, FM and PSK modulation schemes. This paper covers the analysis of first-order TDTL along with design and hardware realization of TDTL based demodulators. TDTL uses a sampling technique which is non-uniform for its implementation. It uses normal and time shifted versions of the incoming signal to detect phase variations thereby allowing several types of demodulation. TDTL realization has wider lock range, reduced complexity, absence of tuning requirements and better immunity to input signal power fluctuations. TDTL method suits this application as a single loop structure can be used to demodulate all required modulation schemes. Here, analysis of TDTL is outlined and demodulators for FSK, FM and PSK signals using TDTL are designed, simulated, implemented and verified on a re-configurable FPGA platform.