Second-order Noise Shaping SAR ADC using 3-input Comparator with Voltage Gain Calibration

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A second-order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for sensor interface applications. It uses a capacitor-resistor hybrid digital-to-analog-converter and two differential integral capacitors to reduce its area. Voltage gain calibration for a 3-input comparator is proposed to maximize the performance of the NS SAR ADC. The proposed second-order NS ADC is designed using a 180-nm CMOS process with a supply of 1.8 V. The simulated SNDR and ENOB are about 87.65 dB and 14.26 bits, respectively, for an analog input signal with a frequency of 12.259 kHz at an over sampling ratio of 8. The area and power consumption of the designed NS SAR ADC are 0.164 mm² and 248 μW, respectively.