Schematic-driven PIC design process considering manufacturing tolerances

Abstract

Inevitable manufacturing tolerances strongly degrade the fabrication yield of photonic integrated circuits (PICs), unless their effect on overall PIC performance characteristics is considered and mitigated during the PIC design process. This is especially true for PICs containing interferometric sub-circuits such as micro-ring optical filters, Mach-Zehnder interferometers, and arrayed waveguide gratings. The problem rapidly increases with the growth of complexity, which is currently observed while designing PICs for large-scale optical interconnects, LIDAR distribution networks, all-optical activation units for artificial neural networks, and multi-ring filters with complex custom transfer functions. Maximizing fabrication yield in such cases is a highly non-trivial task – it requires the development of special design approaches and easy access to statistical performance techniques during the simulations. We present a general-purpose schematic-driven PIC design framework that provides easy access to statistical performance techniques. Our design framework is based on statistical compact simulation models (CSMs) representing the photonic and optoelectronic building blocks (BBs) of foundry-specific process design kits (PDKs). We introduce a special technique that allows identifying critical light paths and applying automated phase compensation inside the models, which significantly simplifies the tolerances analysis, including estimating the final fabrication yield. The analysis of statistical parameter variations due to manufacturing tolerances on-waver and between wavers is supported as well by our presented approach. We demonstrate its application on complex PIC designs comprising of passive and active photonic building blocks.