Scanning electron microscopy studies on switching lateral transistors in integrated circuits

Abstract

A switching phenomenon has been observed in certain lateral geometry transistors in silicon integrated circuits and reported. These devices switch between conducting and non-conducting states and a hypothesis has been proposed to explain the mechanism. It has been suggested that the extension of the collector depletion region within the epitaxial layer increases the resistance of r BB′ causing this effect. This paper describes the use of a scanning electron microscope in the charge collection mode to map the positions of the depletion layers at different bias voltages. Detailed examination of the micrographs has confirmed the proposed theory and has revealed unexpected information about the structure of the transistor.