A numerical analysis of the d.c. performance of small geometry lateral transistors

Abstract

A numerical analysis technique is employed to determine the performance of small lateral geometry transistors in silicon integrated circuits. Results presented include the base transport factor and common-emitter gain of lateral transistors operating at current levels below the onset of base-region high injection. An n + buried layer is introduced and shown to give an improvement in base transport factor but not necessarily in common-emitter current gain. Computer-generated plots indicating areas of high recombination and the distribution of current with the base of the transistor illustrate this effect. The predicted performance of a transistor with an n + buried layer is compared with data from production devices. The program uses a finite-difference method to solve the minority carrier transport and continuity equations within a two-dimensional rectangular mesh. The dependence of carrier mobility on electric field and impurity concentration magnitude is incorporated. The program uses over-relaxation, the optimum factor being determined by Carré's method.