Scaling M-Series™ for Chiplets

Abstract

The semiconductor industry has entered a new era where monolithic integration cannot achieve the economic gains of silicon scaling. The role of chiplets is crucial in this new era by enabling cost reduction through the heterogenous integration of various functions and wafer fab technology nodes. Deca's planar M-Series™ surface is ideal for building highly integrated fan-out SoC (System on Chip) structures. Scaling to $2\mu \mathrm{m}$ lines & spaces and multiple redistribution layers (RDL) provides powerful new possibilities for IC designers. Chiplets can now be fabricated using the optimum wafer fab technology node providing the best performance with the most desirable commercial terms. In combination with Adaptive Patterning™, design rules for M-Series provide large via contacts on fine pitch chip interconnects. The scaling of M-Series for chiplets will be presented in this paper. The 2nd generation of M-Series starts with $2\mu \mathrm{m}$ lines & spaces using laser direct imaging (LDI) with up to four layers of Cu RDL delivering die to die interconnect of >200 wires/mm/layer. This breakthrough in high-density routing is achieved on a simple molded chips-first, chips-up structure without the need for complicated bridge chips in substrates. We will also present a breakthrough in device interface density with $20\mu \mathrm{m}$ pitch full array bond pads made possible with Adaptive Patterning (AP). This paper details the M-Series multi-chiplet fan-out structure with four Cu routing layers, all layers include $2\mu \mathrm{m}$ lines & spaces fabricated using LDI and Adaptive Patterning. The M-Series fan-out structure readily supports through-mold Cu posts if a 3D package on package (3D PoP) structure is required.